1. Field of the Invention
The present invention relates to a standard cell, a standard cell library and a placement method of standard cells for higher integration and area reduction.
2. Description of the Related Art
In the layout design of LSI using an automatic placement & routing tool with on-grid design scheme, terminals of a cell for the communication of input/output signals must be located at the intersections of routing grids in the X and Y directions. In order to satisfy the demand, it is necessary to set a height of the cell to an integral multiple of an interval between the routing grids lined in the Y direction and to set a width of the cell an integral multiple of an interval between the routing grids lined in the X direction. Otherwise, the terminals may not locate at the grid intersection when the cells are placed adjacently with no spacing therebetween. The X direction denotes a direction along a power-supply routing of a standard cell, while the Y direction denotes a direction vertical to the power-supply routing.
According to a conventional method of designing the standard cell recited in No. 61-44444 of the Publication of the Unexamined Japanese Patent Applications, the height and the width of the cell are respectively set to an integral multiple of the interval between the routing grids so that the terminals can always locate at the grid intersection when the cells are placed adjacently with no spacing therebetween. And, the automatic placement & routing tool decide the location of the cells so that their terminals are located at the grid intersection. Then, the automatic placement & routing tool determines the position at which the cell is placed so that the position of the terminal is located at the routing grid intersection.
FIG. 17 is a layout of a standard cell according to a conventional technology. In FIG. 17, C41, C42 and C43 denote a standard cell, T denotes a terminal capable of communicating an input signal or an output signal in the standard cell, and G denotes a gate electrode. The gate electrode G extends in the Y direction because the power-supply wiring is provided in the X direction. FIG. 17 shows that the terminals T cannot locate at the grid intersection when a cell width Lc along the X direction is not an integral multiple of a routing grid interval Lx in the X direction.
None of the widths of the cells C41, C42 and C43 disposed on the upper side in FIG. 17 is the integral multiple of the routing grid interval Lx in the X direction. In the foregoing example, the cells C41, C42 and C43 are identical in order to simplify the description. The terminals T of the cells C41 and C43 locate at the grid intersection, while the terminals T of the cell C42 do not. In other words, the terminals T of the cell C42 fail to be connected in the automatic placement & routing design. In order to avoid the failure, as a general countermeasure, regions R1, R2 and R3 are provided to adjust the cell width to the integral multiple of the routing grid interval in the same manner as cells C51, C52 and C53 disposed on the lower side in FIG. 17. As a result of the adjustment, origins O51, O52 and O53 of the cells C51, C52 and C53 locate at midpoints between the routing grids adjacent to one another along both of the X and Y directions. Accordingly, all of the terminals T can locate at the grid intersection.
However, the regions R1, R2 and R3, which are only provided exclusively for the adjustment in the conventional technology, are normally unnecessary and do not include any device required for a circuit such as a transistor and wiring. As a result, a cell area increases, which is one of the factors obstructing the area reduction of LSI.
Further, in the conventional technology, each cell is placed based on the routing grid in performing the automatic placement in the automatic placement & routing tool with the on-grid design scheme. Therefore, when the cell width is not the integral multiple of the routing grid as in the cells C41, C42 and C43 shown on the upper side in FIG. 17, the cells cannot be placed adjacently with no spacing therebetween as shown on the upper side in FIG. 17. In the automatic placement, the cells are actually placed as shown on the lower side in FIG. 17. Because the cells C41, C42 and C43 are identical in the example shown in FIG. 17, it may be possible to use the widths of the cells C41, C42 and C43 as placement grid in the automatic placement and place the cells shown on the upper side in FIG. 17 in the automatic placement based on the placement grids. However, the automatic placement in the foregoing manner cannot be applied when a plurality of cells to be placed include non-identical cells and are designed so that their widths are arbitrary.
Further, as the miniaturization of the process, a precision in a finished dimension of the gate electrode ultimately obtained is deteriorated by an optical proximity effect when an interval between the gate electrodes and gate lengths of the gate electrodes are irregular in their patterns. When the precision in the finished dimension of the gate electrode is deteriorated, performances of respective transistors of the semiconductor integrated circuit are increasingly inconstant, which leads to an increased variation in a performance of the semiconductor integrate circuit. As a result, a yield ratio is decreased.
In order to solve aforementioned problems, The OPC (optical proximity effect correction) has been widely adopted in each transistor as a conventional technology, however, it takes a larger amount of time to process the OPC in each transistor. Therefore, as recited in No. H10-32253 of the Publication of the Unexamined Japanese Patent Applications, the interval and the length of the gate electrodes in each standard cell are set regular so that the OPC is processed per standard cell in the conventional technology.
FIG. 18 shows a result of the application of the foregoing conventional technology to the standard cell shown in FIG. 17. Like components in FIGS. 17 and 18 are provided with like references. Dummy gate electrodes DG are provided on cell boundaries of standard cells C41′, C41′ and C43′ disposed on the upper side in FIG. 18. These dummy gate electrodes DG are shared between the adjacent standard cells. The gate electrodes G and the dummy gate electrodes DG are respectively equally spaced, and their gate their lengths are equal. Accordingly, the gate electrode pattern, gate length and gate interval (in particular, gate electrode pattern) are regular, not only inside the cell, but also between the cells. In the case of the standard cells C41′, C41′ and C43′ on the upper side in FIG. 18, the pattern of the gate electrode, gate length and gate interval (in particular, the pattern of the gate electrode) are regular not only inside each of the cells but also between the cells. As a result, the precision in the finished dimension of the gate electrode can be improved.
There is no difference between the patterns of the gate length and the gate interval in the case of a single standard cell and in the case of placing the standard cells adjacent to one another. Accordingly, the OPC can be processed in each standard cell.
The OPC can be processed in each of the standard cells C41, C42 and C43 disposed on the upper side in FIG. 17 where the dummy gate electrodes DG are not provided because a distance from the cell boundary of each standard cell to the gate electrode in the closest vicinity and a distance from the cell boundary of an adjacent standard cell to the gate electrode in the closest vicinity can be constant when the distance from the cell boundary of each standard cell to the gate electrode in the closest vicinity is constant.
However, as described, when the regions R1, R2 and R3 for adjusting the cell width to the integral multiple of the routing grid interval are provided, the gate electrode located on the cell boundary of the standard cell cannot be shared. There is a possibility that the dummy electrodes DG are located with less than a minimum interval allowed in a design rule therebetween, which results in an error in the design rule. In order to avoid the foregoing error in the design rule, it is necessary to enlarge the gate length, for example, in the same manner as the dummy gate DG2 disposed on the lower side in FIG. 18.
Though the gate interval in each standard cell can be maintained at the constant level when such the gate length enlargement is executed, the gate length becomes irregular at the dummy gate electrodes DG2, which results in the imprecision of the finished dimension of the gate electrodes. Further, the OPC cannot be processed in each standard cell due to the different gate lengths in the dummy gate electrodes DG in each standard cell and the dummy gate electrodes DG2 adjacent thereto. As a result, the OPC has to be processed with respect to the entire semiconductor integrated circuit.
When the regions R1, R2 and R3 are provided, there is an disadvantage even in the standard cells C51, C52 and C53 disposed on the lower side in FIG. 17 without the dummy gate electrodes DG and DG2 though the distance from the cell boundary of each standard cell to the gate electrode in the closest vicinity in the cell is made constant. To describe the disadvantage, the cell boundary position is changed when the regions R1, R2 and R3 are provided. In that case, though the distance from the cell boundary of each standard cell to the gate electrode in the closest vicinity in the cell is made constant, the distance from the cell boundary to the gate electrode in the closest vicinity becomes inconstant. As a result, the OPC cannot be processed in each standard cell.